NDLI: Low power prescaler implementation in CMOS VLSI

Content Provider	IEEE Xplore Digital Library
Author	Elamaran, V. Reddy, N.B.P. Abhiram, K.
Copyright Year	2012
Description	Author affiliation: Department of ECE, School of EEE, SASTRA University, Thanjavur, Tamilnadu, India (Elamaran, V.) \|\| Department of ECE, School of EEE, SASTRA Univerisity, Thanjavur, Tamilnadu, India (Reddy, N.B.P.; Abhiram, K.)
Abstract	Since the performance of portable electronic products increases continuously with demand, there is a need for low power digital VLSI design. Due to limited backup time of batteries, the operating time of portable electronic products is highly restricted. So the designers now concentrate on low power rather than the speed of the device or system. We implement a frequency divider (prescaler) using different flavors like conventional CMOS logic, pass transistor logic and transmission gate logic styles. Electronic Computer Aided Design (CAD) tools like Micro wind and a DSCH are used in our simulations by which the comparison of power in each style is provided. Micro wind is used a layout editor and DSCH (Digital Schematic) is used as a schematic editor. Results show that the pass transistor logic consumes less power with minimum area and good performance. We used BSTM4 MOSFET model in 0.12 μηι for experimental results.
Starting Page	16
Ending Page	19
File Size	1966394
Page Count	4
File Format	PDF
ISBN	9781467346337
DOI	10.1109/ICETEEEM.2012.6494436
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-12-13
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pass transistor Layout level Low power Prescaler Chip technolgy Frequency divider
Content Type	Text
Resource Type	Article

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