NDLI: A 1 V 2.4/4.8 GHz 4.59 mW CMOS VCO with source degeneration based current mode logic flip-flops for direct conversion receivers

Content Provider	IEEE Xplore Digital Library
Author	Perumal, A. Patra, A. Bhattacharyya, T.K.
Copyright Year	2011
Description	Author affiliation: Dept. of EE, Indian Institute of Technology, Kharagpur, India (Patra, A.) \|\| Dept. of E&ECE, Indian Institute of Technology, Kharagpur, India (Perumal, A.; Bhattacharyya, T.K.)
Abstract	A 1-V 2.4/4.8-GHz 4.59 mW Quadrature Voltage Controlled Oscillator (QVCO) has been designed in 0.18 µm CMOS technology. All-pMOS VCO followed by static frequency divider using source degeneration based D flip-flops is proposed. An accurate small signal analysis model of proposed D flip-flops is provided to estimate the maximum operating frequency of the divider. The advantages of proposed QVCO are analyzed in terms of phase noise and suppress the higher order (≥3) harmonics through linearization. The best overall performance is displayed by the inversion mode pMOS varactor. The proposed QVCO is tuned from 2.4 to 2.5 GHz with a tuning voltage varying from 0 to 1 V, additional 80 MHz increased by switched capacitor array (SCA). Compared to the conventional QVCO, the proposed QVCO shows good $1/ƒ^{3}$ close-in phase noise. The simulated results shows about 6.0 dB, 8.0 dB, 6.0 dB and 0 dB of phase noise improvement at 10 kHz, 100 kHz, 1 MHz and 3 MHz offset from a 2.4 GHz carrier frequency. The input sensitivity of the divider is simulated from 50 mV to 510 mV to achieve the operating frequency varies from 3.0 GHz to 6.2 GHz at 1-V supply.
Starting Page	198
Ending Page	203
File Size	1694867
Page Count	6
File Format	PDF
ISBN	9781424489411
e-ISBN	9781424489435
DOI	10.1109/TECHSYM.2011.5783845
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-14
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Varactor Frequency modulation All-pMOS LC-VCO Switched capacitor array (SCA) Switches Source degeneration Harmonic analysis Threshold voltage Flip-flops
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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