NDLI: 1 V CMOS instrumentation amplifier with high DC electrode offset cancellation for ECG acquisition systems

Content Provider	IEEE Xplore Digital Library
Author	Nanda, C. Mukhopadhyay, J. Mandal, D. Chakrabarti, S.
Copyright Year	2010
Description	Author affiliation: Dept. of E&ECE, IIT Kharagpur, India (Mandal, D.) \|\| G.S.S.S.T, IIT Kharagpur, India (Chakrabarti, S.) \|\| Computer Science and Engineering, IIT Kharagpur, India (Mukhopadhyay, J.) \|\| Siemens Corporate Research & Technology, USA (Nanda, C.)
Abstract	A new circuit topology for a low voltage, low noise instrumentation amplifier (IA) applicable for electrocardiogram signal acquisition system is designed. This circuit is based on the current feedback topology, which is implemented using folded cascode structure at both input and output stages. This helps to sense very low common mode voltage. Achieved input common mode range (ICMR) is 71.43 – 700 mV. DC electrode offset cancellation circuit is realized to remove DC electrode offset along with the low frequency noise. The IA can withstand a high DC electrode offset of ±18 mV. It also has a wide input dynamic range of ±1 µV to ±1 mV. The voltage gain is around 38 dB. It consumes 110 µW power with a supply voltage of 1 V. A high common mode rejection ratio (CMRR) of 80 dB is achieved. The integrated input referred noise is 1.64 µVrms (0.1 Hz – 150 Hz). This design is implemented in 0.18 µm standard CMOS process.
Starting Page	21
Ending Page	25
File Size	1094861
Page Count	5
File Format	PDF
ISBN	9781424459759
e-ISBN	9781424459742
DOI	10.1109/TECHSYM.2010.5469187
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low-noise amplifiers Instruments Folded cascode 1 V CMOS instrumentation amplifier Electrodes Circuit topology Low voltage DC elctrode offset cancellation Feedback circuits Electrocardiography Noise cancellation Circuit noise Signal design
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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