NDLI: High Speed and Memory Efficient Parallel Bit Plane Coding Architecture for JPEG2000

Content Provider	IEEE Xplore Digital Library
Author	Suman, T. Kumar Chatterjee, S. Chakrabarti, I.
Copyright Year	2008
Description	Author affiliation: Dept of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur (Suman, T.; Kumar Chatterjee, S.; Chakrabarti, I.)
Abstract	Bit plane coding (BPC) constitutes an important component of the EBCOT Tier-1 block of JPEG2000 encoder. This paper proposes an efficient parallel hardware structure to implement the computation intensive word level bit plane coding algorithm. The proposed architecture computes the context and decision for all bit planes in parallel. The three coding passes are merged for all bit planes in a scan while the samples are coded in sequence. The proposed parallel BPC architecture offers a speed of 31 over the serial BPC architecture. Its memory requirement is independent of the size of the code block. The speed of the proposed architecture has been shown to be significantly faster than an architecture which has been recently reported in literature. The system architecture has been functionally verified by ModelSim and synthesized by TSMC 0.25 mum vtvt CMOS cell libraries.
Starting Page	232
Ending Page	237
File Size	317887
Page Count	6
File Format	PDF
ISBN	9780769534763
DOI	10.1109/ICVGIP.2008.32
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-16
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Bit plane coding ISO standards Discrete wavelet transforms Parallel architectures Parallel architecture Codeblock Concurrent computing Image coding IEC standards Transform coding Computer architecture Streaming media JPEG2000 encoder Arithmetic
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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