NDLI: Bounding memory interference delay in COTS-based multi-core systems

Content Provider	IEEE Xplore Digital Library
Author	Hyoseung Kim de Niz, D. Andersson, B. Klein, M. Mutlu, O. Rajkumar, R.
Copyright Year	2014
Description	Author affiliation: Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Hyoseung Kim; Mutlu, O.; Rajkumar, R.) \|\| Software Eng. Inst., Carnegie Mellon Univ., Pittsburgh, PA, USA (de Niz, D.; Andersson, B.; Klein, M.)
Abstract	In commercial-off-the-shelf (COTS) multi-core systems, a task running on one core can be delayed by other tasks running simultaneously on other cores due to interference in the shared DRAM main memory. Such memory interference delay can be large and highly variable, thereby posing a significant challenge for the design of predictable real-time systems. In this paper, we present techniques to provide a tight upper bound on the worst-case memory interference in a COTS-based multi-core system. We explicitly model the major resources in the DRAM system, including banks, buses and the memory controller. By considering their timing characteristics, we analyze the worst-case memory interference delay imposed on a task by other tasks running in parallel. To the best of our knowledge, this is the first work bounding the request re-ordering effect of COTS memory controllers. Our work also enables the quantification of the extent by which memory interference can be reduced by partitioning DRAM banks. We evaluate our approach on a commodity multi-core platform running Linux/RK. Experimental results show that our approach provides an upper bound very close to our measured worst-case interference.
Starting Page	145
Ending Page	154
File Size	2726084
Page Count	10
File Format	PDF
ISBN	9781479946914
ISSN	10801812
e-ISBN	9781479948291
DOI	10.1109/RTAS.2014.6925998
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-04-15
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Interference DRAM chips Delays Indexes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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