NDLI: DARTS: Techniques and Tools for Predictably Fast Memory Using Integrated Data Allocation and Real-Time Task Scheduling

Content Provider	IEEE Xplore Digital Library
Author	Sangyeol Kang Dean, A.G.
Copyright Year	2010
Abstract	Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which improve system performance while eliminating such timing variability. Prior work introduced the DARTS approach, which combines static allocation of data into scratchpad memories, with task scheduling for preemptive multi-threaded, hard real-time embedded systems.This study offers several significant contributions. First, it introduces a method to split a stack frame across multiple memory units, offering fine-grain allocation of automatic memory variables with very low run-time overhead. This enables more effective use of fast memory, improving run-times. Second, it introduces the completed tool-chain based on DARTS, which reallocates static and automatic variables across multiple memory banks and now targets the ARM7 architecture. Third, it evaluates the performance improvement from DARTS using experimental results from the code running on real hardware in a preemptively scheduled RTOS-based multi-tasking environment. This hands-on experimental approach ensures a high level of confidence in the results; previous studies have generally stopped at estimating performance rather than building and measuring a real implementation.In our experiments the execution time of each task is reduced up to 24% from the baseline external SRAM configurations. We show that our methods improve task execution time to achieve 37% to 99% of the performance improvement of an ideal unlimited-capacity scratchpad memory system. Finally, we find our allocations provide on average 2/3 of the performance enhancement of the equivalently-sized cache yet with easily-predicted performance.
Starting Page	333
Ending Page	342
File Size	437019
Page Count	10
File Format	PDF
ISBN	9781424466900
ISSN	10801812
e-ISBN	9781424466917
DOI	10.1109/RTAS.2010.36
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-12
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Real time systems Scanning probe microscopy Scratchpad memory Delay Programming profession Preemption threshold scheduling Memory reallocation Runtime Processor scheduling System performance Embedded system Hardware Timing
Content Type	Text
Resource Type	Article

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