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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hentabli, Wahiba Merazka, Fatiha |
| Copyright Year | 2015 |
| Description | Author affiliation: LISIC Laboratory, Telecommunications Department, University USTHB Algiers, Algeria (Hentabli, Wahiba; Merazka, Fatiha) |
| Abstract | A hardware implementation of RSA encryption based on Montgomery algorithm with modular multiplication and systolic array architecture is presented. In this paper, we present an extension of RSA core from 512 key lengths to 1024 key length under hardware platform. The design uses two block multipliers as the main functional unit and Block-RAM as storage unit for the operands. To extend the core from 512 bits to 1024 bits, the design keeps the same IP-Core architecture, it will only adjust the radix used in the multipliers, and number of words to meet the system requirements such as available resources, precision and timing constraints. The architecture, based on the Montgomery modular multiplication algorithm, utilizes a pipelining technique that allows concurrent operation of hardwired multipliers. |
| Starting Page | 448 |
| Ending Page | 453 |
| File Size | 1364806 |
| Page Count | 6 |
| File Format | |
| e-ISBN | 9781908320520 |
| DOI | 10.1109/ICITST.2015.7412140 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-12-14 |
| Publisher Place | United Kingdom |
| Access Restriction | Subscribed |
| Rights Holder | Infonomics Society |
| Subject Keyword | Algorithm design and analysis IP-Core extension RSA Systolic array pipeline Montgomery Powering Ladder Computer architecture Hardware Encryption Internet Acceleration Mathematical model Bit-length key |
| Content Type | Text |
| Resource Type | Article |
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