NDLI: Work, Span, and Parallelism of Transactional Memory Programs

Content Provider	IEEE Xplore Digital Library
Author	Popovic, M. Kordic, B. Basicevic, I.
Copyright Year	2015
Description	Author affiliation: Fac. of Tech. Sci., Univ. of Novi Sad, Novi Sad, Serbia (Popovic, M.; Kordic, B.) \|\| Inst. RT-RK, Univ. of Novi Sad, Novi Sad, Serbia (Basicevic, I.)
Abstract	Recent developments indicate that after more than a decade of intensive pioneer work, both in academia and industry, transactional memory might finally become a standard part of the mainstream processors. Intel Haswell and IBM Blue Gene are first such processors indicating this trend. However, it is still not clear what would be the right performance metric and how it could be estimated and measured for a given TM program. This paper suggests that parallelism should be used as the performance metric and it proposes the method for estimating and measuring parallelism within a given TM program. In order to illustrate usage of the proposed method, we applied it to two realistic TM programs, namely Simple Bank and Race Bank. As the main result of our analysis we derived the lower and the upper bounds on parallelism for these two TM programs. Both programs have the same upper bound on parallelism, which varies from 2 to 14 when the number of read-write transactions increases from 100 to 1000, but Race Bank has better performance, because its lower bound on parallelism is constantly 1, whereas the lower bound on parallelism for Simple Bank is decreasing from 0.06 to 0.04.
Starting Page	59
Ending Page	66
File Size	229765
Page Count	8
File Format	PDF
ISBN	9781467379670
DOI	10.1109/ECBS-EERC.2015.18
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-08-27
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Measurement Computer languages Analytical models Upper bound Program processors Estimation Parallel processing Programming Concurrency control Parallel architectures Modeling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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