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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chanda, J. Kanjilal, A. Sengupta, S. Bhattacharya, S. |
| Copyright Year | 2009 |
| Description | Author affiliation: B.P. Poddar Institute of Management & Technology, Kolkata, WestBengal, India (Chanda, J.; Kanjilal, A.; Sengupta, S.) || National Instititute of Technology, DurgaPur , West Bengal, India (Bhattacharya, S.) |
| Abstract | UML being semi formal in nature, it lacks formal syntax and hence automated verification of analysis and design specifications cannot be done. Verification at early phases of SDLC has gained significant importance because of the possibility of early error detection resulting in reduced costs and time to market. To address this, in this paper we propose a formal grammar for the three of the commonly used UML diagrams - Use Case diagram, which is used to capture functional requirement; Activity diagram, which is used to diagrammatically depict the textual descriptions, or flow of events of use case diagram, and Class diagram, which is used to depict the structural aspect of design. In this paper, we have proposed a framework for verification of the diagrams, which includes syntactic correctness, inter-diagram consistency and requirement traceability. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 829281 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424450510 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-12-14 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Costs Object oriented modeling Unified modeling language Time to market Programming Software safety Parse tree Phase detection Computer science Production Context free grammar UML formalization Context modeling |
| Content Type | Text |
| Resource Type | Article |
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