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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Cavalcanti, M.C. Alves, R.N. da Silva, E.R.C. Lima, A.M.N. Jacobina, C.B. |
| Copyright Year | 2000 |
| Description | Author affiliation: UFPB, Campina Grande, Brazil (Cavalcanti, M.C.) |
| Abstract | In this proposed paper, a reduced-loss PWM strategy for three-phase inverters that synchronizes the clamping period of one of the phases with the current peak in the phase is extended to the case of a three-phase pulsed DC-link voltage (PDCLV) type inverter. Such strategy, which takes into account the influence of the load power angle on losses, has been employed with an existing soft-switched PDCLV inverter. This topology has been shown to produce less losses than the hard-switched inverter version. The technique is easily implemented by a hybrid modulator scheme that leads to a systematic and straight approach to generate any continuous or discontinuous PWM strategy. Simulated and experimental results demonstrate the validity of the proposed technique. |
| Starting Page | 1980 |
| Ending Page | 1987 |
| File Size | 613722 |
| Page Count | 8 |
| File Format | |
| ISBN | 0780364015 |
| ISSN | 01972618 |
| DOI | 10.1109/IAS.2000.882149 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2000-10-08 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Space vector pulse width modulation Pulse width modulation inverters Support vector machines Phase modulation Switching loss Voltage Pulse width modulation Pulse inverters Topology Frequency synchronization |
| Content Type | Text |
| Resource Type | Article |
| Subject | Industrial and Manufacturing Engineering Control and Systems Engineering Electrical and Electronic Engineering |
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