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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yi Liu Cheng Lei Hongqi Zhang |
| Copyright Year | 2015 |
| Description | Author affiliation: Henan Key Lab. of Inf. Security, Zhengzhou Inf. Sci. & Technol. Inst., Zhengzhou, China (Yi Liu; Cheng Lei; Hongqi Zhang) |
| Abstract | Since faults in the configurations of flow tables arise commonly in Open Flow network, this paper proposes a tool called MR-Verifier verifying network properties. Based on MapReduce, MR-Verifier can verify network properties in parallel, providing fast non-real-time verification. On the base of it, when network states change, MR-Verifier can conduct verification incrementally, realizing real-time verification. To accelerate verification process further, it converts operations on matching fields of rules with the help of atomic predicates. Theoretical analysis and experimental results demonstrate that MR-Verifier is about 40 times faster than Hassel on the average, and performs verifying within tens or hundreds of microseconds per link up while Net Plumber and Veriflow use several seconds. Additionally, MR-Verifier is much more space efficient than Hassel. |
| Starting Page | 546 |
| Ending Page | 553 |
| File Size | 577107 |
| Page Count | 8 |
| File Format | |
| e-ISBN | 9781467392006 |
| DOI | 10.1109/CyberC.2015.57 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2015-09-17 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis Verifying network properties Ports (Computers) Solids Control systems Real-time systems OpenFlow network IP networks Time complexity MapReduce |
| Content Type | Text |
| Resource Type | Article |
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