NDLI: PVTOL: Providing Productivity, Performance and Portability to DoD Signal Processing Applications on Multicore Processors

Content Provider	IEEE Xplore Digital Library
Author	Hahn Kim Rutledge, E. Sacco, S. Mohindra, S. Marzilli, M. Kepner, J. Haney, R. Daly, J. Bliss, N.
Copyright Year	2008
Description	Author affiliation: MIT Lincoln Lab., Lexington, MA (Hahn Kim; Rutledge, E.; Sacco, S.; Mohindra, S.; Marzilli, M.; Kepner, J.; Haney, R.; Daly, J.; Bliss, N.)
Abstract	PVTOL provides an object-oriented C++ API that hides the complexity of multicore architectures within a PGAS programming model, improving programmer productivity. Tasks and conduits enable data flow patterns such as pipelining and round-robining. Hierarchical maps concisely describe how to allocate hierarchical arrays across processor and memory hierarchies and provide a simple API for moving data across these hierarchies. Functors encapsulate computational kernels; new functors can be easily developed using the PVTOL API and can be fused for more efficient computation. Existing computation and communication technologies that are optimized for various architectures are used to achieve high performance. PVTOL abstracts the details of the underlying processor architectures to provide portability. We are actively developing PVTOL for Intel, PowerPC and Cell architectures and intend to add support for more computational kernels on these architectures. FPGAs are becoming popular for accelerating computation in both the high performance computing (HPC) and high performance embedded computing (HPEC) communities. Integrated processor-FPGA technologies are now available from both HPC and HPEC vendors, e.g. Cray and Mercury Computer Systems. We plan to support FPGAs as co-processors in PVTOL. Finally, automated mapping technology has been demonstrated with pMatlab. We plan to begin implementing automated mapping in PVTOL next year. Similar to PVL, as PVTOL matures and is used in more projects at Lincoln, we plan to propose concepts demonstrated in PVTOL to HPEC-SI for adoption into future versions of VSIPL++.
Starting Page	327
Ending Page	333
File Size	671968
Page Count	7
File Format	PDF
ISBN	9781424433230
DOI	10.1109/DoD.HPCMP.UGC.2008.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Productivity Embedded computing Multicore processing Array signal processing High performance computing Computer architecture Signal processing Kernel Field programmable gate arrays Electronics packaging
Content Type	Text
Resource Type	Article

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