NDLI: Future scaling of Si based microelectronics and the role of consortia

Content Provider	IEEE Xplore Digital Library
Author	Jammy, R.
Copyright Year	2011
Description	Author affiliation: Materials and Emerging Technologies, Sematech, USA (Jammy, R.)
Abstract	Semiconductor technology and its relentless scaling are at the core of many of the revolutionary gains humanity has witnessed in the last few decades. Future scaling options are promising, although complex and costly. Planar, Si-based materials integration for ever smaller devices has matured to heterointegration of non-Si materials today, and rapidly, scaling is moving to the 3rd dimension for devices and interconnects. Patterning technologies are pushing the limits of immersion-based deep UV technologies and are at the cusp of EUV technologies. Looking farther beyond, several options like nano imprint and directed self assembly are emerging to address cost and throughput issues. Functionality per unit area per unit cost continues to be aggressively pushed, and move to 450mm wafer size is along this trend. Concurrent to all these changes, functionally driven scaling - where traditional CMOS/memory elements are combined with non-CMOS devices to realize complex system on a chip (SOC), and perhaps system in a package (SIP) are being pursued. These changes present enormous opportunities for the industry, but are significant transitions to new technologies that require coordination across chip makers, supply chain, design and system houses. Consortia like SEMATECH play a critical role in enabling these transitions. Many infrastructural issues, standards and protocols for successful introduction of new technology transitions to high volume manufacturing are addressed to minimize cost and risk.
Starting Page	1
Ending Page	1
File Size	30633
Page Count	1
File Format	PDF
ISBN	9781457704154
e-ISBN	9781457704161
DOI	10.1109/TTM.2011.6005167
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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