NDLI: Low power, high frequency, free dead zone PFD for a PLL design

Content Provider	IEEE Xplore Digital Library
Author	Majeed, K.K.A. Kailath, B.J.
Copyright Year	2013
Description	Author affiliation: Indian Inst. of Inf. Technol. Design & Manuf.(IIITD&M), Chennai, India (Majeed, K.K.A.; Kailath, B.J.)
Abstract	Two novel phase frequency detectors PFD1 and PFD2 have been proposed in this paper. PFD1 has been designed with 15 transistors while PFD2 with 8 transistors. It has been observed that both these PFDs could operate up to frequencies three to five times higher than that of conventional PFD. It has also been observed that the power dissipation is reduced by 80.3% and 99.2 % in PFD1 and PFD2 respectively. In addition to these, area of the circuit has been reduced up to 64.9 % for PFD1 and up to 81.4 % for PFD2 when compared with conventional PFDs. The phase noise also has been reduced to - 161.8 dBc/Hz and -142.1 dBc/Hz for PFD1 and PFD2 respectively. Prototype has been designed in Cadence virtuoso environment and implemented using GPDK090 library of 180 nm technology with a supply voltage of 1.8 V. The reset process has been completely removed in both the designs thereby eliminating the blind zone and speeding up the acquisition process. Both the designs have been proposed for high speed, low power and low jitter applications.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	1
Ending Page	4
File Size	681333
Page Count	4
File Format	PDF
ISBN	9781467361057
e-ISBN	9781467361040
DOI	10.1109/FTFC.2013.6577768
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-20
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Phase Locked Loop Charge pumps Phase frequency detector Jitter Dead zone Transistors Phase locked loops Voltage control
Content Type	Text
Resource Type	Article

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