NDLI: An efficient FPGA implementation of Gaussian mixture models based classifier: Application to face recognition

Content Provider	IEEE Xplore Digital Library
Author	Neggazi, M. Bengherabi, M. Boulkenafet, Z. Amira, A.
Copyright Year	2013
Description	Author affiliation: Sch. of Comput., Univ. of the West Scotland, Paisley, UK (Amira, A.)
Abstract	This work aims to propose an efficient hardware/software system fo guassian mixture model (GMM) parts-based topology modeling for face identification and verification. Following its great success in speaker recognition, The GMM approach was extended to face recognition providing a good trade-off in terms of complexity, performance and robustness. Despite its reduced complexity compared to other statistical modeling techniques like hiden markov model (HMM) and its variants. The GMM scoring module still to be computationally intensive algorithm consisting of a series of complex tasks executed in sequential order. This constraint limits its suitability for real-time pattern recognition embedded applications. This paper presents an efficient hardware implementation of embedded GMM based classifier. Reconfigurable system in the form of field programmable gate arrays (FPGA) is deployed to embed the hardware part of the proposed system. Furthermore a design of exponential calculation circuit is proposed for the best compromise between effectiveness and complexity. Approximations are also developed to reduce the hardware complexity. The developed system performs the identification process of an unknown input pattern over 200 models in 2.3 seconds, our performance evaluation indicates that a speedup of around S.IX can be achieved over an optimized software implementation running on a 3.3GHz core i3 processor. A results precision of $10^{-2}$ is obtained after performing the GMM calculation using the proposed hardware/software system.
Starting Page	367
Ending Page	371
File Size	227622
Page Count	5
File Format	PDF
ISBN	9781467355407
DOI	10.1109/WoSSPA.2013.6602393
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-05-12
Publisher Place	Algeria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded systems Face recognition FPGA Hidden Markov models GMM Computer architecture Hardware Vectors Complexity theory Reconfigurable architectures Face Field programmable gate arrays
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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