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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | DeYi Shi Xien Ye |
| Copyright Year | 2013 |
| Description | Author affiliation: Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China (DeYi Shi; Xien Ye) |
| Abstract | As a video image display interface standard, VGA interface has been widely used in the embedded system. Due to the lack of professional VGA display controller in most embedded systems, splash screen, even blank screen problems may appear while displaying the high-resolution video image. The design illustrates the implement method of VGA display controller, which combines CPLD and SRAM. First, the design stores data that gets from the processor in the SRAM and then reads them out in form of VGA display interface standard into D/A converter which will convert the data into analog signals to display. The whole operation above is controlled by CPLD. So such a design can effectively solve the problems caused by insufficient bandwidth in the displaying, what's more, it can reduce the pressure of the CPU. The article not only gives the internal detailed design of CPLD, which includes generation of VGA timing signal, finite state machine and logic control, but also presents analysis of practical tests rendering. The system has been successfully used in the digital language teaching products. |
| Starting Page | 579 |
| Ending Page | 582 |
| File Size | 183717 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781467348935 |
| DOI | 10.1109/ISDEA.2012.141 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-01-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computers VGA Random access memory Verilog Writing CPLD Timing SRAM Standards Monitoring Clocks |
| Content Type | Text |
| Resource Type | Article |
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