NDLI: PXIe Based High-Speed Transmission System Design and Implementation

Content Provider	IEEE Xplore Digital Library
Author	Yu Hongqi Zhou Zhou Yin Qinghong Li Nan Sun Zhaolin Xu Xin
Copyright Year	2010
Abstract	PXIe protocol is a novel high-speed transmission bus protocol in industry. PXIe not only offers high performance up to 500MB/s bandwidth (4 lines), but also is completely compatible with PCI Express protocol. However, the current implementation in FPGA can not make full use of its advantages. The paper describes a direct memory access system to improve the real bandwidth of PXIe bus. For direct memory access can operate either as a master or a slave device for PXIe bus, two combined modules are designed to deal with two conditions respectively. Furthermore, a buffer sub-system utilizing DDR2 SDRAM is proposed to satisfy the demands of both high data throughput rate and large capacity in the high-speed environment. Measured experimental results confirm that the direct memory access system increases the bandwidth of original data transfer rate from 100MB/s to 500MB/s with very low bit error rate.
Starting Page	95
Ending Page	98
File Size	193746
Page Count	4
File Format	PDF
ISBN	9781424483334
DOI	10.1109/ISDEA.2010.440
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-13
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Protocols PCIe eXtension for instrumentation Aerospace electronics FIFO Master Slave Bandwidth DMA DDR2 SDRAM SDRAM IP networks Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

High bandwidth memory interface design based on DDR3 SDRAM and FPGA

An FPGA implementation for a high-speed optical link with a PCIe interface

Communication-centric design for FMC based I/O system

Optimized design of UART IP soft core based on DMA mode

Development of high-speed data acquisition card based on PXI Express Bus

Design and Implementation of a Reused Interface

Optimized FPGA-based DDR2 SDRAM controller

AXI-based SpaceFibre IP core implementation

DDR2/DDR3-based ultra-rapid reconfiguration controller

PXIe Based High-Speed Transmission System Design and Implementation

Similar Documents

High bandwidth memory interface design based on DDR3 SDRAM and FPGA

An FPGA implementation for a high-speed optical link with a PCIe interface

Communication-centric design for FMC based I/O system

Optimized design of UART IP soft core based on DMA mode

Development of high-speed data acquisition card based on PXI Express Bus

Design and Implementation of a Reused Interface

Optimized FPGA-based DDR2 SDRAM controller

AXI-based SpaceFibre IP core implementation

DDR2/DDR3-based ultra-rapid reconfiguration controller

PXIe Based High-Speed Transmission System Design and Implementation