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Content Provider | IEEE Xplore Digital Library |
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Author | Oliveira, D.L. Curtinhas, T. Bompean, D. Ferreira, L.S. Romano, L. |
Copyright Year | 2012 |
Description | Author affiliation: Departamento de Engenharia Elétrica, Centro Universitário da FEI São Bernardo do Campo - SP - Brazil (Romano, L.) || Divisão de Engenharia Eletrônica, Instituto Tecnológico de Aeronáutica, São José dos Campos - SP - Brazil (Oliveira, D.L.; Curtinhas, T.; Bompean, D.; Ferreira, L.S.) |
Abstract | In a synchronous digital system the activity of the clock signal is a major consumer of energy. It consumes 15% to 45% of energy consumed. Reducing the activity of the clock signal produces a reduction of energy considered, but also reduces clock skew problems and iteration electromagnetic. An interesting strategy is the synchronous digital system to operate in the transitions of both edges of the clock signal (double-edge triggered — DET), as this allows a 50% reduction in the frequency of the clock signal, but having the same processing rate data. In this paper we propose a method for synthesis of synchronous digital systems that operate on both edges of the clock signal, but the state memory is composed only of flip-flops that are sensitive to a single edge of the clock signal (single-edge triggered flip-flops — SET-FF). |
Starting Page | 1 |
Ending Page | 4 |
File Size | 345037 |
Page Count | 4 |
File Format | |
ISBN | 9781467312073 |
e-ISBN | 9781467312080 |
DOI | 10.1109/LASCAS.2012.6180347 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2012-02-29 |
Publisher Place | Mexico |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Solid modeling Digital systems Radiation detectors Registers Synchronization Clocks Flip-flops |
Content Type | Text |
Resource Type | Article |
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