NDLI: Integration of cellular front end modules on advanced high resistivity SOI RF CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Gianesello, F. Durand, C. Pilard, R. Petit, D. Penard, J. Jan, S. Gloria, D. Rauber, B. Raynaud, C.
Copyright Year	2011
Description	Author affiliation: STMicroelectronics, TR&D, STD, 850 avenue Jean Monnet, 38926 Crolles, France (Gianesello, F.; Durand, C.; Pilard, R.; Petit, D.; Penard, J.; Jan, S.; Gloria, D.; Rauber, B.) \|\| CEA Leti, avenue des martyrs, 38000 Grenoble, France (Raynaud, C.)
Abstract	Since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning front end module (FEM) integration on silicon [1]. In this quest, SOI technology has emerged as the technology of choice [2] since the antenna switch and the power amplifier (PA) have been successfully integrated on SOI [3, 4]. In this paper, we will focus our investigation on high performance passive functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, balun, harmonic filter, diplexer and directional coupler have been achieved in a 130 nm SOI CMOS technology. Measured performances are clearly competitive with most commercially available Integrated Passive Device (IPD) solutions, which paves the way of FEM silicon SOCs.
Starting Page	29
Ending Page	32
File Size	407724
Page Count	4
File Format	PDF
ISBN	9781424484164
e-ISBN	9781424484157
DOI	10.1109/PAWR.2011.5725381
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-01-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	GSM Coupler Harmonic filter Balun Finite element methods SOI Front End Module Silicon on insulator technology Radio frequency Semiconductor device modeling Integrated passive CMOS technology CMOS integrated circuits High Resistivity Diplexer
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Integration of multi-standard front end modules SOCs on high resistivity SOI RF CMOS technology

Small-size low losses GSM and DCS harmonic filters integrated in a low cost 130 nm high resistivity SOI CMOS technology

0.35 dB loss 20 dB coupling directional coupler integrated in 130 nm CMOS SOI technology targeting 3G PA SOC

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Integration of cellular front end modules on advanced high resistivity SOI RF CMOS technology

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