NDLI: Integration of LwIP Stack over Intel(R) DPDK for High Throughput Packet Delivery to Applications

Content Provider	IEEE Xplore Digital Library
Author	Rajesh, R. Ramia, K.B. Kulkarni, M.
Copyright Year	2014
Description	Author affiliation: Intel® Technol. Pvt. Ltd., Bangalore, India (Rajesh, R.; Ramia, K.B.) \|\| Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol. Karnataka, Mangalore, India (Kulkarni, M.)
Abstract	Performance of generic operating system like Linux based IP stacks on multicore processors is much less than that of the purpose built IP stacks from the commercial stack vendors which typically run on a SoC/ASICs/Network processor. The issue of under-utilization of hardware resources arises from the fact that the generic IP stacks operate with much higher overhead, thereby decreasing the overall system performance compared to the capability of the underlying hardware. With Intel multicore processors, it's possible to transition from using discrete architectures per major workload (application, control, packet, and signal processing) to a single architecture that consolidates the workloads into a more scalable and simplified solution. This is possible, in large part, due to the Intel Data Plane Development Kit (Intel DPDK), a set of data plane libraries that can improve packet processing performance by up to ten times compare to processing capabilities by traditional OS. Users can integrate their own custom IP stacks with the Intel DPDK and get the advantage of accelerated performance of the Intel DPDK to their applications. This paper explains integration of a version of Light Weight TCP/IP (LwIP) stack with Intel DPDK to extend high packet processing capabilities of Intel DPDK to application layer level and measuring the performance capabilities of DPDK-LwIP network stack.
Starting Page	130
Ending Page	134
File Size	537851
Page Count	5
File Format	PDF
e-ISBN	9781479969654
DOI	10.1109/ISED.2014.34
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-15
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processors Protocols Packet processing Intel® DPDK LwIP Computer architecture Throughput Libraries IP networks Kernel Message systems
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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