NDLI: Enhancement of Production Pattern Development Methodology and Best Practices

Content Provider	IEEE Xplore Digital Library
Author	Ghosh, P. John, C. Gupta, A. Siripurapu, V.
Copyright Year	2013
Description	Author affiliation: Freescale Semicond. India Pvt. Ltd., India (Ghosh, P.; John, C.; Gupta, A.; Siripurapu, V.)
Abstract	Execution and stabilization of production patterns on ATE (Automatic Test Equipment) is becoming a challenging task with the increasing complexity of SoC(s)(System on chip). The conventional approach for production pattern development involves coding of test in HDL/HVL (e.g. system verilog), running the simulation at RTL level (or gate level netlist) to generate the vcd (Value Change Dump). The vcd is then converted to tester specific format to run on ATE/Virtual Tester. Many times these patterns go through regeneration process in order to stabilize across PVT (Process, Voltage, Temperature). E-fuse & MBIST production patterns take considerable time on ATE especially for SoC which have large number of electronic fuses (e.g. 1024 bits or more) & memories. Some of these patterns gate the start of post-silicon validation. With conventional methodology, the major challenges are the pattern generation time (it involves extensive usage of compute resources), inability to modify on the fly and information exchange across teams. To address the above challenges, we have developed a methodology (“scenario”) for fuse/MBIST patterns which eliminates vcd generation and enables on the fly tweaking and re-use. The patterns implemented with this approach, is re-usable across SoC(s) for BIST and e-fuse. In this paper, we will discuss this methodology and its impact. In applying this methodology, we have seen significant reduction on pattern bring-up time (~80%), silicon bring-up time (~80%) and pattern iteration count (<;2.6%) in C293 [1]. In addition, we will highlight some of the best practices followed as part of production pattern development, which helped us to reduce product characterization cycle by ~ 30% for C293 [1].
Starting Page	153
Ending Page	157
File Size	207817
Page Count	5
File Format	PDF
e-ISBN	9781479923014
DOI	10.1109/ISED.2013.37
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fuses SoC Built-in self-test E-fuse Pattern Generation ATE Best Practices for Production Patterns Development Functional Production Pattern Generation Production Silicon MBIST Pattern Generation Timing System-on-chip Pins
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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