NDLI: A comparative study on low power adders using microwind EDA tool

Content Provider	IEEE Xplore Digital Library
Author	Sayapaneni, P. Elamaran, V.
Copyright Year	2014
Description	Author affiliation: Dept. of Electron. & Commun. Eng., SASTRA Univ., Thanjavur, India (Sayapaneni, P.; Elamaran, V.)
Abstract	From the past few years a variety of low power adders have been proposed to reduce the overall power consumption of micro-electronic systems. The role of adders are important in almost all fields of engineering and applied sciences. With the help of low power adders, all the other systems which make use of adders may dissipate less power. This study presents a detailed comparison between various low power 1-bit full adders. This study focuses mainly on the comparisons among conventional Complementary Metal Oxide Semiconductor (CMOS) adder, bridge style adder, transmission gate adder, square root based adder and static energy recovery full adder, etc. All the simulation results are done using Digital Schematic (DSCH) editor and the functionality is verified using the Microwind layout editor tool. The sole objective of this study to conclude with a better estimate and ease in selecting a low power adder for the required application.
Starting Page	1
Ending Page	5
File Size	285894
Page Count	5
File Format	PDF
ISBN	9781479939749
e-ISBN	9781479939756
DOI	10.1109/ICCIC.2014.7238457
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-18
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Simulation Layout Bridge circuits Transmission gate Logic gates Bridge adder Microwind CMOS integrated circuits Layout editor Transistors CMOS adder Adders
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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