NDLI: TDC SAR algorithm with continuous disassembly (SAR-CD) for time-based ADCs

Content Provider	IEEE Xplore Digital Library
Author	Ragab, K.O. Mostafa, H. Eladawy, A.
Copyright Year	2015
Description	Author affiliation: Electron. & Commun. Eng. Dept., Cairo Univ., Cairo, Egypt (Ragab, K.O.; Mostafa, H.; Eladawy, A.)
Abstract	This paper introduces a new algorithm and circuit design of Time-to-Digital Converter(TDC) with modified Successive Approximation Register(SAR) algorithm. This design enables continuous pulse disassemble. The input pulse is absolutely compared to pulses of widths proportional to Vfs/2, Vfs/4..Vfs/N, and each bit is evaluated independent of the previous bit result. Then bits correction is applied after the sample evaluation. A 4bit case study circuit is realized using TSMC CMOS 65nm design technology. The design demonstrated 3.67 Effective Number Of Bits (ENOB) for a sampling frequency of 666 MS\s.
Starting Page	1
Ending Page	4
File Size	1773527
Page Count	4
File Format	PDF
e-ISBN	9781479917716
DOI	10.1109/ICEAC.2015.7352197
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-24
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Pulse generation Time-based analog-to-digital converter Software defined radio Successive approximation register Computer architecture Logic gates Delays Circuit synthesis Clocks Time-to-digital converter
Content Type	Text
Resource Type	Article

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TDC SAR algorithm with continuous disassembly (SAR-CD) for time-based ADCs