NDLI: A novel 10-Bit high-throughput two-stage TDC with reduced power and improved linearity

Content Provider	IEEE Xplore Digital Library
Author	Abdelmejeed, M. Guindi, R. Abdel-Moneum, M.
Copyright Year	2013
Description	Author affiliation: Intel Corp., Hillsboro, OR, USA (Abdel-Moneum, M.) \|\| Dept. of Microelectron. Syst. Design, Nile Univ. Nile Univ. -, Giza, Egypt (Abdelmejeed, M.; Guindi, R.)
Abstract	This paper introduces a new architecture that improves the throughput of the two-stage Time to Digital Converter (TDC). An oscillator-based TDC is used for conversion. The time residue from the first stage is generated directly after the stop signal is asserted and saved in the form of phase-shift between two oscillating signals. Instead of using two stages, an asynchronous control block is implemented to reuse the same hardware block for both the first and second conversion stages. This technique not only reduces power and area, but also eliminates the TDC nonlinearity due to the mismatch between the two stages. A throughput of 400 MS/s for a 10bit resolution, a time resolution of 2.6 ps, a DNL of 0.38, and an INL of 0.402 are achieved.
Starting Page	50
Ending Page	54
File Size	438220
Page Count	5
File Format	PDF
ISBN	9781479925438
DOI	10.1109/ICEAC.2013.6737636
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-16
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low-Power TDC Time Difference Amplifier Linearity Computer architecture Time to Digital Converter (TDC) Throughput Improved Linearity Delays Two-Stage TDC Synchronization Oscillators Signal resolution
Content Type	Text
Resource Type	Article

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