NDLI: Multiple instruction sets architecture (MISA)

Content Provider	IEEE Xplore Digital Library
Author	Karaki, H. Akkary, H.
Copyright Year	2011
Description	Author affiliation: Department of Electrical and Computer Engineering, American University of Beirut, FEA, Beirut, Lebanon (Karaki, H.; Akkary, H.)
Abstract	In the computer hardware industry, there are currently two highly successful instruction set architectures (ISAs): the CISC X86 ISA which is an established standard architecture in the personal computer and server markets, and the RISC ARM ISA which is currently used in many ultra-mobile computing devices, such as smart-phones and tablets. Platforms that run one standard ISA cannot run the other ISA application binaries without recompiling the source code. We are investigating the technical feasibility of designing an energy-efficient multiple instruction sets architecture (MISA) processor that can run both X86 and ARM binaries. We propose an approach in which special decoders interpret the binary instructions of the running ISA and translates them to a native target machine ISA that executes within the processor pipeline. We discuss the completed initial stage of our work involving the design of XAM, an X86 hardware binary interpreter for a MISA processor that runs native ARM instructions, and describe our design in detail. We present performance and energy simulation results of our MISA processor design for a set of synthetic benchmarks including Dhrystone 2.1, measured using the ARM SimpleScalar microarchitecture and power simulator. We also discuss design issues of an ARM to X86 hardware interpreter we are currently developing. We expect the completed X86-to-ARM design and the current ARM-to-X86 work to lay a foundation for designing a well optimized processor having a new native ISA that can run efficiently both X86 and ARM binaries, using direct hardware interpretation.
Starting Page	1
Ending Page	6
File Size	584293
Page Count	6
File Format	PDF
ISBN	9781467304665
e-ISBN	9781467304658
e-ISBN	9781467304641
DOI	10.1109/ICEAC.2011.6136696
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-30
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithms Computer architecture Benchmark testing Hardware Software Registers Decoding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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