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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hentati, M. Aoudni, Y. Nezan, J. Abid, M. Deforges, O. |
| Copyright Year | 2011 |
| Description | Author affiliation: INSA/IETR, 20, av des Buttes de coesmes CS 14315 F-35043 RENNES, France (Hentati, M.; Nezan, J.; Deforges, O.) || ENIS/CES, Route Soukra B.P. 1173, 3038 Sfax, Tunisie (Aoudni, Y.; Abid, M.) |
| Abstract | With the rapid evolution of technology, the latest FPGA architectures such as Virtex series of Xilinx introduced a new feature called Dynamic Partial Reconfiguration (DPR). This technique allows designer to configure a portion of the FPGA while other parts continue to run on the same FPGA. The design of an embedded system based on the DPR functionality is still complex and tedious. The MPEG consortium proposes the Reconfigurable Video Coding (RVC) technology. RVC provides a high level description of video decoders described as a set of interconnected Functional Units. This paper studies the use of the RVC technology for the specification of an application and the design of a system based on the DPR functionality. In this paper, we study the Inverse Quantization (IQ) algorithm of an MPEG-4 decoder and how to switch between the MPEG-2 and the H263 IQ algorithms using RVC and DPR. This simple and concrete case study highlights the DPR restrictions to take into account in MPEG RVC description in order to use the DPR. |
| Starting Page | 1 |
| Ending Page | 7 |
| File Size | 369600 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781457706202 |
| e-ISBN | 9781457706219 |
| e-ISBN | 9781457706196 |
| DOI | 10.1109/DASIP.2011.6136863 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-11-02 |
| Publisher Place | Finland |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Algorithm design and analysis FPGA Quantization Dynamic Partial Reconfiguration Decoding Transform coding Computer architecture RVC framwork RVC-CAL language Hardware Field programmable gate arrays MPEG-RVC Inverse Quantization |
| Content Type | Text |
| Resource Type | Article |
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