NDLI: TADC: Thread-aware Divide-and-Conquer policy to manage shared cache

Content Provider	IEEE Xplore Digital Library
Author	Wei Yin Junmin Wu Xiufeng Sui Yingqi Jin Xiaodong Zhu
Copyright Year	2010
Description	Author affiliation: School of Computer Science and Technology, University of Science and Technology of China, Hefei, 230027, China (Wei Yin; Junmin Wu; Xiufeng Sui; Yingqi Jin; Xiaodong Zhu)
Abstract	Modern Chip Multiprocessors (CMPs) contain multiple cores in a single chip and these cores share last-level cache (LLC). When applications with different memory access behaviors compete for the shared LLC, conventional Least Recently Used (LRU) management policy leads to performance degradation. Applications with different memory access behaviors compete for the shared LLC in different ways, and many researchers have proposed various techniques to improve the performance of the entire CMPs. In this work, we propose a new cache replacement policy (we name it the TADC) that eliminates the side effects brought by streaming applications and judiciously allocate precious LLC resources to those applications that can benefit from additional cache ways. This new policy equally divides each cache set into several subsets whose number is equal to the number of applications running on the CMPs and maps each subset to each application. It detects the memory access behaviors of different applications in different intervals. And it determines different insertion and promotion policies in different subsets according to their owners' memory access behaviors in the last interval. This new policy can also support inter-core capacity stealing. The proposed TADC improves the total Instruction Per Cycle (IPC) throughput as much as 24.3% and 5.94% (on average 7.48% and 3.00%) over the baseline LRU policy for Dual-Core workloads and Quad-Core workloads respectively.
Starting Page	701
Ending Page	704
File Size	793258
Page Count	4
File Format	PDF
ISBN	9781424468348
e-ISBN	9781424468379
DOI	10.1109/ICISS.2010.5655528
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-22
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computers Divide-and-Conquer Last-level Cache Computational modeling Chip Multiprocessors Replacement Policy
Content Type	Text
Resource Type	Article

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