NDLI: 2-D Separable discrete Hartley transform architecture for efficient FPGA resource

Content Provider	IEEE Xplore Digital Library
Author	Sharma, V.K. Agrawal, R. Pati, U.C. Mahapatra, K.K.
Copyright Year	2010
Description	Author affiliation: Dept. of Electronics & Comm. Engg. National Institute of Technology, Rourkela, India-769008 (Sharma, V.K.; Agrawal, R.; Pati, U.C.; Mahapatra, K.K.)
Abstract	Discrete cosine transform (DCT) is usually used in JPEG based image transform coding. This paper presents separable 2-D discrete Hartley transform (SDHT) and its Distributed Arithmetic (DA) based hardware architecture as an alternate to DCT in transform based coding of image compression. The proposed DA architecture for 1-D DHT has very less computations as compared to existing 1-D DCT. The proposed DHT architecture implemented in FPGA indicates a significant hardware savings as compared to FPGA resources used in an efficient memory based DA approach. The additional advantage of SDHT is that its inverse transform is same as forward transform with a constant division. This is demonstrated through a Xilinx FPGA XC2VP30 device.
Starting Page	236
Ending Page	241
File Size	153783
Page Count	6
File Format	PDF
ISBN	9781424490332
e-ISBN	9781424490349
DOI	10.1109/ICCCT.2010.5640432
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-17
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image coding Discrete Hartley Transform Discrete Cosine Transform DH-HEMTs Hardware JPEG Distributed Arithmetic Discrete cosine transforms Offset Binary Coding MODFETs
Content Type	Text
Resource Type	Article

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