NDLI: Compact thermal modeling for package design with practical power maps

Content Provider	IEEE Xplore Digital Library
Author	Zao Liu Tan, S.X.-D. Hai Wang Quintanilla, R. Gupta, A.
Copyright Year	2011
Description	Author affiliation: Department of Electrical Engineering, University of California, Riverside, 92521, USA (Zao Liu; Tan, S.X.-D.; Hai Wang)
Abstract	This paper proposes a new thermal modeling method for package design of high-performance microprocessors. The new approach builds the thermal behavioral models from the given accurate temperature and power information by means of the subspace method. The subspace method, however, may suffer predictability problem when the practical power is given as a number of power maps where power inputs are spatially correlated. We show that the input power signal needs to meet some dependency requirements to ensure model predictability. We develop a new algorithm, which generates independent power maps to meet the spatial rank requirement and can also automatically select the order of the resulting thermal models for the given error bounds. Experimental results validates the proposed method on a practical microprocessor package constructed via COMSOL software under practical power signal inputs.
Starting Page	1
Ending Page	5
File Size	955207
Page Count	5
File Format	PDF
ISBN	9781457712227
e-ISBN	9781457712210
DOI	10.1109/IGCC.2011.6008577
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Training Temperature measurement System identification
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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