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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ertürk, M.C. Güvenc, I. Arslan, H. |
| Copyright Year | 2010 |
| Description | Author affiliation: DOCOMO Communications Laboratories USA, Inc., 3240 Hillview Avenue, Palo Alto, CA, 94304 (Güvenc, I.) || Dept. of Electrical Engineering, University of South Florida, Tampa, FL, 33620 (Ertürk, M.C.; Arslan, H.) |
| Abstract | In this paper we analyze various user assignment and scheduling policies for neigbouring femtocell networks. The trade-off between capacity maximization and fairness is investigated and a combined user assignment and proportional fair (PF) scheduling procedure for a femtocell gateway is proposed. The flexibility of the proposed architecture in terms of capacity and fairness is studied via various simulation scenarios. It is shown that by changing parameters in the proposed method one can play-out between fairness and capacity in a femtocell network. In order to decrease the number of the handovers between femtocells, we propose that a femtocell user should be scheduled with the same femtocell base station for a duration of superframe, i.e, cell re-selection should be done in every superframe. The performance of the combined user assignment and PF scheduling scheme is investigated under different superframe considerations and it is shown that a wide range of performance results (in terms of capacity, fairness, handover frequency) could be achieved. |
| Starting Page | 54 |
| Ending Page | 59 |
| File Size | 361916 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424491179 |
| e-ISBN | 9781424491162 |
| DOI | 10.1109/PIMRCW.2010.5670520 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-09-26 |
| Publisher Place | Turkey |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Femtocell networks HeNB Proportional fairness Capacity Interference Bandwidth Computer architecture Logic gates Indexes Signal to noise ratio Gateway scheduling algorithms |
| Content Type | Text |
| Resource Type | Article |
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