NDLI: VLSI implementation of single bit control system processor with efficient code density

Content Provider	IEEE Xplore Digital Library
Author	Ranjith, J. Muniraj, N.J.R. Renganayahi, G.
Copyright Year	2010
Description	Author affiliation: Dept of ECE, Sri Sakthi Inst of Engg & Technology, Coimbatore, TN, India (Renganayahi, G.) \|\| Dept of ECE, Anna University, Coimbatore, TN, India (Ranjith, J.) \|\| HOD, Dept of ECE, Karpagam College of engg, Coimbatore, TN, India (Muniraj, N.J.R.)
Abstract	Abstract-This paper describes a novel single bit control system processor with efficient code density in System on Chip (SOC) and mixed signal applications. Advanced process technology nowadays enables hundreds of million transistors to be integrated onto a single chip, making system-on-a-chip designs more feasible than ever. Such SOC chips usually consist of various components such as analog-to-digital (ADCs) and digital-to-analog (DACs) converters, Phase locked loops (PLLs), random logic, memory, processors, and so on. Delta-Sigma (ΔΣ) modulator is frequently used in the Conversion of signals from analog or digital form into bit streams at very high sampling rate. Single Bit control system processor that uses this modulation technique is a small and fast application-specific processor in SOC and mixed signal applications. Another increasing concern in processor design is improved Code density, since it reduces the need for the scarce resource memory and also implicitly improves further important design Parameters like power consumption and performance. A dictionary based data compression technique which provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty is introduced here. This may also reduce the power Consumption, since memory consumes a significant amount of Control system processor's power
Starting Page	103
Ending Page	108
File Size	1079196
Page Count	6
File Format	PDF
ISBN	9781424477692
e-ISBN	9781424477708
DOI	10.1109/ICCCCT.2010.5670536
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-07
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Code compression 1-bit processing ΔΣ modulation VLSI Random access memory Process control System-on-chip (SOC) Table lookup Control system processor Delay Read only memory Runtime Memory management Mixed signal Look Ahead Decision Feedback Code density
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Efficient Code Density Through Look-up Table Compression

Efficient DFT Strategy for Complex Mixed-Signal SoC

Design optimization of DWT structure for implementation of image compression techniques

High density optical disk system using D8-15 modulation code and new signal-processing techniques

A Novel $DeltaSigma$ Control System Processor and Its VLSI Implementation

Lossless compression of G.711 speech using only look-up tables

A memory compression scheme for modular arithmetic

Systolic RNS arithmetic using feedback shift logic

Efficient VLSI architecture of medium throughput AES encryption

VLSI implementation of single bit control system processor with efficient code density

Similar Documents

Efficient Code Density Through Look-up Table Compression

Efficient DFT Strategy for Complex Mixed-Signal SoC

Design optimization of DWT structure for implementation of image compression techniques

High density optical disk system using D8-15 modulation code and new signal-processing techniques

A Novel $DeltaSigma$ Control System Processor and Its VLSI Implementation

Lossless compression of G.711 speech using only look-up tables

A memory compression scheme for modular arithmetic

Systolic RNS arithmetic using feedback shift logic

Efficient VLSI architecture of medium throughput AES encryption

VLSI implementation of single bit control system processor with efficient code density