NDLI: Simultaneous improvement of area, delay, and fault tolerance in quantum circuits

Content Provider	IEEE Xplore Digital Library
Author	Nabizadeh, Z. Sedighi, M. Zamani, M.S.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Eng. & Inf. Technol., Amirkabir Univ. of Technol., Tehran, Iran (Nabizadeh, Z.; Sedighi, M.; Zamani, M.S.)
Abstract	Fault tolerance is a necessity for successful realization of quantum circuits. Achieving fault tolerance in quantum circuits is more complicated than classic circuits due to their inherent characteristics such as error continuum, destruction of quantum state after measurement, and no-cloning. Adding fault tolerance should incur a reasonably minimal overhead in latency and area. In this paper, a new approach for implementation of fault tolerant quantum circuits is proposed. The correction blocks are arranged in such a way that the overall circuit area and delay are reduced. This will also lead to a reduction in error distance in the circuit. The correctness of the proposed approach is mathematically proven in the paper. Experimental results confirm the analytical expectations and show an average improvement of 47.8% in terms of delay, 17.6% in terms of area, and 47.8% in terms of error distance.
Sponsorship	IEEE Iran Sect.
Starting Page	59
Ending Page	64
File Size	305457
Page Count	6
File Format	PDF
ISBN	9781479905621
e-ISBN	9781479905652
DOI	10.1109/CADS.2013.6714238
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-10-30
Publisher Place	Iran
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Fault tolerant systems Computer architecture Error detection and correction Logic gates Benchmark testing Delays Fault tolerant quantum circuit Quantum measurement Equations
Content Type	Text
Resource Type	Article

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