NDLI: A high-level architecture for efficient packet trace analysis on GPU co-processors

Content Provider	IEEE Xplore Digital Library
Author	Nottingham, A. Irwin, B.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., Rhodes Univ., Grahamstown, South Africa (Nottingham, A.; Irwin, B.)
Abstract	This paper proposes a high-level architecture to support efficient, massively parallel packet classification, filtering and analysis using commodity Graphics Processing Unit (GPU) hardware. The proposed architecture aims to provide a flexible and efficient parallel packet processing and analysis framework, supporting complex programmable filtering, data mining operations, statistical analysis functions and traffic visualisation, with minimal CPU overhead. In particular, this framework aims to provide a robust set of high-speed analysis functionality, in order to dramatically reduce the time required to process and analyse extremely large network traces. This architecture derives from initial research, which has shown GPU co-processors to be effective in accelerating packet classification to up to tera-bit speeds with minimal CPU overhead, far exceeding the bandwidth capacity between standard long term storage and the GPU device. This paper provides a high-level overview of the proposed architecture and its primary components, motivated by the results of prior research in the field.
Starting Page	1
Ending Page	8
File Size	807370
Page Count	8
File Format	PDF
ISBN	9781479908080
DOI	10.1109/ISSA.2013.6641052
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-08-14
Publisher Place	South Africa
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Graphics processing units Prototypes Information security Computer networks Arrays Indexes Acceleration Data mining GPGPU
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A high-performance Click-based packet classifier on GPU

Efficient Parallel Muti-pattern Matching Using GPGPU Acceleration for Packet Filtering

GPU acceleration of finding frequent patterns over large biological sequence

GPregel: A GPU-Based Parallel Graph Processing Model

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings

Accelerating MapReduce on a coupled CPU-GPU architecture

An efficient STT-RAM last level cache architecture for GPUs

Advantages and GPU implementation of high-performance indexed DNA search based on suffix arrays

Power Efficient MapReduce Workload Acceleration Using Integrated-GPU

A high-level architecture for efficient packet trace analysis on GPU co-processors

Similar Documents

A high-performance Click-based packet classifier on GPU

Efficient Parallel Muti-pattern Matching Using GPGPU Acceleration for Packet Filtering

GPU acceleration of finding frequent patterns over large biological sequence

GPregel: A GPU-Based Parallel Graph Processing Model

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings

Accelerating MapReduce on a coupled CPU-GPU architecture

An efficient STT-RAM last level cache architecture for GPUs

Advantages and GPU implementation of high-performance indexed DNA search based on suffix arrays

Power Efficient MapReduce Workload Acceleration Using Integrated-GPU

A high-level architecture for efficient packet trace analysis on GPU co-processors