NDLI: An efficient and reliable 1.5-way processor by fusion of space and time redundancies

Content Provider	IEEE Xplore Digital Library
Author	Jun Yao Watanabe, R. Yoshimura, K. Nakada, T. Shimada, H. Nakashima, Y.
Copyright Year	2011
Description	Author affiliation: Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma 630-0192, Japan (Jun Yao; Watanabe, R.; Yoshimura, K.; Nakada, T.; Shimada, H.; Nakashima, Y.)
Abstract	Recently, many architectural level mechanisms such as dual or triple modular redundancies (DMR or TMR) have been included in high-end microprocessors to tolerate the continuously increasing electronic error rates along the process technology advancing direction. However, hardware in these space redundancy based systems is usually not well-balanced or it has been over-designed. In particular, it requires twice the hardware to achieve a reliable execution in a single issue processor, hence resulting in an area/performance efficiency decreased by half. This efficiency will be even worse when the redundancy is extended to multi-issue processors, which have already exchanged some area for performance enhancement. In this research, we propose a reliable 1.5-way superscalar processor by including time redundancy into the original space redundancy systems. This is usually not preferred when performance and permanent failure are considered. However, by this fusion of space and time redundancies, it is possible to perform dual executions on a triple-pipeline processor. Special working schemes have also been defined to distribute every dual-execution onto different units for both transient and permanent failure toleration. This architecture achieves better performance than a single issue DMR processor while balancing more area/performance than a dual-issue DMR processor. Our performance simulation and area synthesis results show that under equal reliability, the proposed scheme can have 22.6% better performance/area efficiency than a traditional DMR 2-way superscalar processor.
Starting Page	69
Ending Page	74
File Size	1076260
Page Count	6
File Format	PDF
ISBN	9781457703744
e-ISBN	9781457703751
e-ISBN	9781457703737
DOI	10.1109/DSNW.2011.5958838
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-27
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Redundancy Aerospace electronics Hazards Hardware Registers Transient analysis
Content Type	Text
Resource Type	Article

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