NDLI: A pre-registered buffering method for iSER-based storage over IP SAN

Content Provider	IEEE Xplore Digital Library
Author	Hsu-Cheng Lin Han-Chiang Chen Shun-Chieh Lin
Copyright Year	2010
Description	Author affiliation: Dept. of Digital Home Service Application Technology, Home Networking Technology Center, ITRI South, Bldg. R1, No.31, Gongye 2nd Rd., Annan District, Tainan City 709, Taiwan (Hsu-Cheng Lin; Han-Chiang Chen; Shun-Chieh Lin)
Abstract	Previous work shows that iSER-based storage is a data-intensive system that involves heavy checking for the data integrity during transmission. In this work, we address several issues and develop schemes to speed up the iSER-based storage system for the read/write operations, including iSCSI and iSER modules integration, pre-registered buffer region design for iSER module, and data receiver thread design for iSCSI module. By integrating iSCSI and iSCSI Extensions to RDMA (iSER, a RDMA-capable protocol) running over Ammasso RDMA adapter, this work can reduce latency and increase throughput compared with pure iSCSI architecture. The experimental results show that the proposed system with low latency and high throughput is promising less CPU usage. Less CPU resources usage would be helpful for the network transmission, especially using low power CPUs, such as resource-limited embedded systems.
Starting Page	1
Ending Page	4
File Size	1197738
Page Count	4
File Format	PDF
ISBN	9781424469864
e-ISBN	9788988678206
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-11
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	AICIT
Subject Keyword	Computer interfaces Storage area networks Buffer storage ISCSI Embedded system ISER Access protocols Computer architecture Storage Network Throughput Delay
Content Type	Text
Resource Type	Article

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