NDLI: Batch-Pipelining for H.264 Decoding on Multicore Systems

Content Provider	IEEE Xplore Digital Library
Author	Tang-Hsun Tu Chih-Wen Hsueh
Copyright Year	2010
Abstract	Pipelining has been applied in many area to improve performance by overlapping executions of computing stages. However, it is difficult to apply on H.264/AVC decoding in frame level, because the bitstreams are encoded with lots of dependencies and little parallelism is left to be explored. Therefore, many researches can only adopt hardware assistance. Fortunately, pure software pipelining can be applied on H.264/AVC decoding in macroblock level with reasonable performance gain. However, the pipeline stages might need to synchronize with other stages and incur lots of extra overhead. Moreover, the overhead becomes relatively larger as the stages themselves are executed faster with better hardware and software optimization. We first group multiple stages into larger groups as ”batched” pipelining to execute concurrently in multicore systems. The stages in different groups might not need to synchronize to each other so that it incurs little overhead and can be highly scalable. Therefore, a novel effective batch-pipeline (BP) approach for H.264/AVC decoding on multicore systems is proposed. Moreover, because of its flexibility, BP can be used with other hardware approaches or software technologies to further improve performance. To optimize our approach, we analyze how to group the macroblocks and derive close-form formulas to guide the grouping. We also conduct various experiments on various bitstreams to verify our approach. The results show that it can speed up to 93% and achieve up to 249 and 70 FPS for 720P and 1080P resolutions, respectively, on a 4-core machine over a published optimized H.264 decoder.We believe our batch-pipelining approach creates a new effective direction for multimedia software codec development.
Starting Page	553
Ending Page	553
File Size	88871
Page Count	1
File Format	PDF
ISBN	9781424464258
ISSN	10680314
e-ISBN	9781424464265
DOI	10.1109/DCC.2010.57
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Multicore processing Pipeline processing Automatic voltage control Hardware Parallel processing Software performance Data compression Multimedia systems Multimedia computing Multicore Pipelining Optimization Multimedia H.264
Content Type	Text
Resource Type	Article
Subject	Computer Networks and Communications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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