NDLI: 1-cycle code decompression circuitry for performance increase of Xtensa-1040-based embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Lekatsas, H. Henkel, J. Jakkula, V.
Copyright Year	2002
Description	Author affiliation: NEC USA Inc., Princeton, NJ, USA (Lekatsas, H.; Henkel, J.; Jakkula, V.)
Abstract	Code compression is known to be an effective technique to reduce the instruction memory size of an embedded system. However code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. In this paper we describe our design of the world's first running prototype of a 1-cycle code decompression circuitry that decompresses Xtensa 1040 instructions on-the-fly. The circuitry is a standalone unit that does not require any modifications on the Xtensa 1040 processor core. We observed an average code size reduction of about 35% of programs running on the system and an average of 45% of performance increase due to the increased bandwidth and memory hierarchy effects.
Sponsorship	IEEE Solid State Circuits Soc. Electron Devices Soc
Starting Page	9
Ending Page	12
File Size	490797
Page Count	4
File Format	PDF
ISBN	0780372506
DOI	10.1109/CICC.2002.1012756
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Embedded system Bandwidth Prototypes Reduced instruction set computing Circuit testing National electric code Presses Cost function Process design System testing
Content Type	Text
Resource Type	Article

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