NDLI: Micromachined high-Q inductors in 0.18 /spl mu/m Cu interconnect low-K CMOS

Content Provider	IEEE Xplore Digital Library
Author	Lakdawala, H. Zhu, X. Luo, H. Santhanam, S. Carley, L.R. Fedder, G.K.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Lakdawala, H.)
Abstract	Spiral inductors fabricated in a 0.18 /spl mu/m 6-level copper interconnect low-K dielectric process are described. A post-CMOS maskless micromachining process compatible to copper interconnect and low-k dielectric CMOS has been developed to create inductors suspended 100 /spl mu/m above the substrate with sidewall oxide removed. Such inductors have higher quality factors as substrate losses are eliminated by silicon removal and have higher self-resonant frequency due to removal of inter-turn dielectrics. Micromachined inductors have the potential to extend the useful operational frequency range of CMOS RF circuits. Quality factors of greater than 7 were obtained at 5.5 GHz for inductors with silicon undercut and inter-turn oxide removed, compared to a Q of 4 for inductors having only their inter-turn oxide removed but without silicon undercut.
Sponsorship	IEEE Solid State Circuits Soc.
Starting Page	579
Ending Page	582
File Size	507433
Page Count	4
File Format	PDF
ISBN	0780365917
DOI	10.1109/CICC.2001.929846
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-05-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Inductors Dielectric substrates Copper Integrated circuit interconnections Silicon Q factor Dielectric losses Frequency Spirals Micromachining
Content Type	Text
Resource Type	Article

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