NDLI: Substrate-induced high-frequency noise in deep sub-micron MOSFETs for RF applications

Content Provider	IEEE Xplore Digital Library
Author	Kishore, S.V. Chang, G. Asmanis, G. Hull, C. Stubbe, F.
Copyright Year	1999
Description	Author affiliation: Silicon Wave, San Diego, CA, USA (Kishore, S.V.)
Abstract	We present results from high-frequency noise measurements on NMOS devices fabricated in a 0.5-/spl mu/m epi-based CMOS process. These noise measurements at RF frequencies reveal the existence of substrate-induced high-frequency noise in transistors operating in the saturation regime. The substrate-induced noise is independent of the transistor bias conditions, but is strongly dependent on the geometry of the device and the MOS gate-to-bulk capacitance. A new ac noise model for CMOS devices operating at RF frequencies presented here shows good conformity to measurements. Its implications are emphasized via the design of a low-noise amplifier (LNA) operating at 2 GHz. The minimum achievable noise-figure (NF) can be higher by as much as 0.6 dB due to this substrate-induced high-frequency noise.
Starting Page	365
Ending Page	368
File Size	393571
Page Count	4
File Format	PDF
ISBN	0780354435
DOI	10.1109/CICC.1999.777307
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-05-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	MOSFETs Noise measurement Radio frequency MOS devices CMOS process Geometry Capacitance Semiconductor device modeling Frequency measurement Low-noise amplifiers
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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