NDLI: Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

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List of contributors

A 100 MHz FPGA based floating point adder

FPGA implementation of a reconfigurable microprocessor

VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM

CMAP-Technology mapping for multiplexor based FPGA architectures using certificate of generic Boolean function

Technology mapping and circuit depth optimization for field programmable gate arrays

Efficient Boolean matching in technology mapping with very large cell libraries

VIPER: A 25-MHz, 100-MIPS peak VLIW microprocessor

Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

FPA10-A 4 MFLOP floating point coprocessor for ARM

A programmable clock generator with 50 to 350 MHz lock range for video signal processors

A low power trainable analogue neural network classifier chip

A VLSI array processor for neural network algorithms

Timing-driven resynthesis by rescheduling and encoding

Synthesis of throughput-optimized multichip architectures

A high level synthesis interface to erasable programmable logic devices

Generalized ILP scheduling and allocation for high-level DSP synthesis

Dominance based methodologies for multiple output CMOS combinational gates synthesis

A framework for fault-tolerant microarchitecture synthesis

An analog circuit technique for finding the median

Low-voltage fully-differential CMOS switched-current filters

A 5th order bilinear elliptic switched-current filter

Integrated continuous-time filter design

Introducing redundancy in field programmable gate arrays

Optimized reconfigurable cell array architecture for high-performance field programmable gate arrays

A dual granularity and globally interconnected architecture for a programmable logic device

Advantages of heterogeneous logic block architecture for FPGAs

A 150-mW dynamic power 10-ns 22V10 programmable logic device (PLD)

A 10 ns, 4000 gate, 160 pin CMOS EPLD developed on a 0.8 /spl mu/m process

PREP benchmarks for programmable logic devices

Macromodeling BiCMOS gates for circuit optimization

An efficient macromodel for static CMOS multi-port memories

An FFT-based approach to including non-ideal ground planes in a fast 3-D inductance extraction program

Mixed-mode simulation of phase-locked loops

Mixed-level circuit and device simulation on a distributed-memory multicomputer

Design and implementation of a prototype hybrid simulation environment

Acceptance sampling: An efficient, accurate method for estimating and optimizing parametric yield

PAS: A stand alone placement annotation system for high speed designs

Modifying the netlist after placement for performance improvement

Performance-driven layout through device sizing

Delay and area optimization for discrete gate sizes under double-sided timing constraints

A high density datapath layout generation method under path delay constraints

Skew reduction in clock trees using wire width optimization

A combined eigenvector tabu search approach for circuit partitioning

A 24 Mbit/s 1,7 read channel combo for disk-drive applications

A 3-5.5 V CMOS 32 Mb/s fully-integrated read channel for disk-drives

CMOS implementation of a Viterbi detector for hard disk drives

A 7 MB/sec (65 MHz), mixed-signal, magnetic recording channel DSP using partial response signaling with maximum likelihood detection

A high performance digital read channel for hard disk drives using PRML techniques

An integrating servo demodulator for hard disk drives

Video compression and VLSI

A half-pel precision motion estimation processor for NTSC-resolution video

A motion video compression LSI with distributed arithmetic architecture

A single chip multistandard video codec

CMOS image sensors for multimedia applications

3.3 V, novel circuit techniques for a 2.8-million-transistor BiCMOS RISC processor

A 64-bit adder by pass transistor BiCMOS circuit

A CMOS signed multiplier using wave pipelining

A 2.4-ns, 16-bit, 0.5-/spl mu/m CMOS arithmetic logic unit for microprogrammable video signal processor LSIs

An outline font rendering processor with an embedded RISC CPU for high-speed hint processing

A 300-MHz, 16-bit, 0.5-/spl mu/m BiCMOS digital signal processor core LSI

Hexagonal sensor with imbedded analog image processing for pattern recognition

Analog design automation: Where are we? Where are we going?

A multi-representational design data capture system

A spreadsheet interface for analog design knowledge capture and re-use

A system for analog circuit design that stores and re-uses design procedures

Flow-driven graphical user interface for parametric and statistical design optimization

SYSCHECK: A user-programmable mixed-mode verification tool

MOSFET modeling for analog circuit CAD: Problems and prospects

A robust physical and predictive model for deep-submicrometer MOS circuit simulation

Advanced VLSI circuit simulation using the BSIM

Characterization, modeling and minimization of transient threshold voltage shifts in MOSFETs

Performance optimization of analog integrated circuits by device sizing and its application to pseudosynthesis

ACAD: A hierarchical approach to CMOS design analysis

Low-frequency symbolic analysis of large analog integrated circuits

A new efficient transient noise analysis technique for simulation of CCD image sensors or particle detectors

Cost, power, and parallelism in speech signal processing

Digital filter design for compact on-chip oversampling A/D conversion

A reconfigurable video ghost cancelling filter chip

HDTV data carrier separation using a multiplexing filter

VINCI: VLSI implementation of the new secret-key block cipher IDEA

Programmable facsimile image processor including fuzzy-based decision

1.8V CMOS analog compander and 80 dB dynamic range

A low-power TDMA PCS wireless modem chip in 0.6 /spl mu/m 3V CMOS

A 200 MHz CMOS digital radio frequency memory chip with analog output

A direct-sequence spread spectrum transceiver chip

A programmable VLSI neural network processor for digital communications

A 60-Mbaud adaptive transversal equalizer in 1.0-/spl mu/m CMOS for QAM digital modems

A 300 MHz BiCMOS serial data transceiver

Optimum stacked layout for analog CMOS ICs

An improved algorithm for transistors pairing for compact layout of non-series-parallel CMOS networks

Performance-driven compaction for analog integrated circuits

Power distribution synthesis for analog and mixed-signal ASICs in RAIL

Resistance extraction along the current flow

HCNC: High Capacity Netlist Compare

Finite-pole macromodels of transmission lines for circuit simulation

Rapid simulation of substrate coupling effects in mixed-mode ICs

AWEswit: A switched capacitor circuit simulator

Frequency-domain analysis of switched capacitor circuits containing nonidealities

A one-million-circuit CMOS ASIC logic family

0.5 /spl mu/m 1 M gate CMOS SOG

A 30-ps jitter, 3.6-/spl mu/s locking, 3.3-volt digital PLL for CMOS gate arrays

A 51K-gate low power ECL gate array family with metal-compiled and embedded SRAM

Interface techniques for embedding custom mega cells in a gate array

A planar type EEPROM cell structure by standard CMOS process for integration with gate array, standard cell, microprocessor and for neural chips

A fully-complementary BiCMOS array for mixed analog/digital applications

High performance BiCMOS technology

A BiCMOS 0.8 /spl mu/m process with a toolkit for mixed-mode design

A 0.8-/spl mu/m BiCMOS technology for ASIC applications

0.3 /spl mu/m mixed analog/digital CMOS technology for low-voltage operation

A modular merged technology process including submicron CMOS logic, nonvolatile memories, linear functions, and power components

Design and optimization of high-voltage CMOS devices compatible with a standard 5 V CMOS technology

Integration of high voltage transistors into a 1.5 micron CMOS process for LCD driver applications

A 64 kB BiCMOS cache controller and memory (CCM)

A high performance/low power 16 K-byte 4-way set associative integrated cache macro

An adjustable output driver with self-recovering Vpp generator for 4 M/spl times/16 DRAM

1.5 V high speed read operation and low power consumption circuit technology for EPROM and flash-EEPROM

A 3.3 V ASIC for mixed voltage applications with shut down mode

A 200-MHz 8-Kb SRAM macro for video applications

A programmable power metering chip

CMOS fuzzy logic controller in current mode

Test of a 622 MHz hybrid module for ATM network using a 200 MHz validation station

A new design for testability method: Clock line control design

FUNTASSI: A functional test generation assistant

IDDQ test results on a digital CMOS ASIC

A new BIST scheme for CMOS PLAs

Special applications of the voting model for bridging faults

Computation of exact random pattern detection probability

Multi-frequency zero-jitter delay-locked loop

Cell based fully integrated CMOS frequency synthesizers

A high precision (+/- 100 ppm) CMOS clock generator for optimum sampling of analog RGB data [in LCD panel display]

A BiCMOS 50-MHz voltage-controlled oscillator with quadrature outputs

CMOS sampler with 1 Gbit/s bandwidth and 25 ps resolution

1.16 GHz dual-modulus 1.2 /spl mu/m CMOS prescaler

Metastability behavior of mismatched CMOS flip-flops using state diagram analysis

A 100 MHz 8 bit CMOS interpolating A/D converter

An enhanced successive-approximation circuit for A/D conversion

A CMOS triple 9-bit 180 MHz DAC for HDTV applications

A single-chip stereo audio codec

A high resolution sigma-delta modulator with extended dynamic range

A BiCMOS time interval digitizer for high-energy physics instrumentation

Output buffer with on-chip compensation circuit

An integrated GaAs receiver for optoelectronic signal processing and interconnection

Computer aided design and packaging optoelectronic systems with free space optical interconnects

Computer aided conceptual design of multichip systems

Multilevel optimization of high speed VLSI interconnects using decomposition

An efficient signal redistribution algorithm for MCM

Crosstalk-minimum layer assignment

The impact of hot-electron degradation on CMOS analog subcircuit performance

Circuit reliability of hot electron induced degradation in high speed CMOS SRAM

Reliability assessment of self-timed VLSI circuits

STRECH: Self testing reliability evaluation chip

Improved quality and reliability using operating extremes test methods

Built-in current mode circuits for I/sub ddq/ monitoring

Hot-carrier reliability design guidelines for CMOS logic circuits

Special Applications Of The Voting Model For Bridging Faults

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Self-checking and recovering microprocessor G100FTS for fault-tolerant systems

Content Provider	IEEE Xplore Digital Library
Author	Terayama, F. Korematsu, J. Kitamura, F. Hinata, J. Enomoto, T.
Copyright Year	1993
Description	Author affiliation: Mitsubishi Electric Corp., Itami, Hyogo, Japan (Terayama, F.)
Abstract	The architecture and implementation of an application-specific processor, the G100FTS, designed for fault-tolerant systems are described. The G100FTS integrates the core processor and the support module for fault-tolerant operation. The core processor is the 32-b microprocessor Gmicro/100 based on the TRON specifications. The support module provides a mechanism of error detection, a rollback operation that recovers a processor from a transient fault, diagnosis of faulty processors, and reconfiguration of a single processor system to make it operate continuously. The G100FTS drastically reduces the component count of a system and provides high system reliability. The G100FTS performs all the fault-tolerant operations in hardware and requires no dedicated programs for fault tolerance. The chip contains 805K transistors within a chip size of 13 mm /spl times/ 14 mm. A 1.0-/spl mu/m, double-metal CMOS technology was used.
File Size	482565
File Format	PDF
ISBN	0780308263
DOI	10.1109/CICC.1993.590405
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-05-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Fault tolerance CMOS technology Application specific processors Process design Fault tolerant systems Fault detection Fault diagnosis Reliability Hardware
Content Type	Text
Resource Type	Article

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