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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Khan, M.H. Rengarajan, S. |
| Copyright Year | 2007 |
| Abstract | Traditional image composition for output display involves accessing discrete overlay images and blending them together as per the requirement of the application. Increased display sizes and number of overlays increases the memory bandwidth. For low power SOCs with integrated display controllers display traffic has an adverse effect on the application's performance and power consumption. Based on the overlay positions and blending method used for output image composition only one overlay may occlude another fully or partially. Hardware display accelerators can take advantage of such occlusion to reduce memory bandwidth without compromising image quality. This paper presents strategies for such reduction for some of the popular blending algorithms. A bandwidth efficiency metric n is defined and is evaluated for each of the presented schemes. Savings in memory bandwidth leads to higher performance of applications and also reduced power at the memory interface and hence increasing battery lifetime. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 1213136 |
| Page Count | 2 |
| File Format | |
| ISBN | 1424407621 |
| DOI | 10.1109/ICCE.2007.341345 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-01-10 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Displays Bandwidth Hardware Image quality Pixel Engines Energy consumption Batteries Postal services Streaming media |
| Content Type | Text |
| Resource Type | Article |
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