NDLI: A 0.18 /spl mu/m CMOS SoC of a front-end hardware platform for DVD-multi recorders

Content Provider	IEEE Xplore Digital Library
Author	JooSeon Kim GoangSeog Choi HyunJeong Park YoungJun Ahn MyungSik Kim KiSun Cho TaeHo Lee MyungHee Han JumHan Bae HyunSoo Park YoonWoo Lee SooYul Jung JoongEon Seo DongHo Shin
Copyright Year	2005
Description	Author affiliation: Samsung Electron. Co., Suwon, South Korea (JooSeon Kim; GoangSeog Choi; HyunJeong Park; YoungJun Ahn; MyungSik Kim; KiSun Cho; TaeHo Lee; MyungHee Han; JumHan Bae; HyunSoo Park; YoonWoo Lee; SooYul Jung; JoongEon Seo; DongHo Shin)
Abstract	This work presents a 0.18 /spl mu/m CMOS system on a chip (SoC) that is a hardware platform for the front-end of DVD-multi recorders (FESOC). It has one 32 bit RISC CPU and one 16 bit DSP as well as most of the necessary components for DVD recorders, except for an analog front end (AFE) and some memories. The necessary building blocks are a partial response channel maximum likelihood detector (PRML), a servo signal processor (SERVO), write strategy controller (WSC), a data processor (DP), an AT-attachment packet interface (ATAPI), and a micro computer unit (MCU). Using a three-layered bus architecture enables this FESOC to work well with a 16 bit-wide bus at 67 MHz for 8/spl times/ DVD operation, and to be implemented with a short development time. The FESOC is fabricated in 0.18 /spl mu/m 1-poly 5-metal CMOS technology. It contains 8.4 million transistors in a 46 mm/sup 2/ die and consumes 1.4 W with a channel clock of 209.28 MHz in 8/spl times/ operation mode.
Starting Page	53
Ending Page	54
File Size	257225
Page Count	2
File Format	PDF
ISBN	0780388380
DOI	10.1109/ICCE.2005.1429713
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-01-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware System-on-a-chip DVD Maximum likelihood detection Servomechanisms CMOS technology Reduced instruction set computing Digital signal processing chips Partial response channels Detectors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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