NDLI: Application of a negative sweep voltage to control gate of fresh flash memory devices to facilitate threshold voltage test measurement

Content Provider	IEEE Xplore Digital Library
Author	Cha, C.L. Chor, E.F. Gong, H. Teo, T.H. Zhang, A.Q. Chan, L.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore (Cha, C.L.)
Abstract	The immediate threshold voltage (V/sub th/) measurements conducted on fresh flash memory devices gained no definite results: the obtained cell drain current (I/sub d/) versus applied gate voltage Old plots for the devices were oscillating and erratic. Suspected cause for this abnormal phenomenon arises from the random to-and-fro movements of the embedded positive charges present in the flash devices, across the reoxidized nitrided oxide (ONO) interpoly dielectric layer in the availability of electric fields. Application of a negative sweep voltage to the control gate of the fresh memory devices prior to the conduction of the V/sub th/ tests, however, seems to produce smooth I/sub d/ vs. V/sub g/ curve plots which yield repeatable as well as reasonable V/sub th/ values. The acquirement of such electrical results readily suggest the partial or full removal of the initial embedded positive charges, which were present in the devices as a result of charging from plasma exposure during the etching/implantation fabrication steps, by the applied gate potential.
Starting Page	253
Ending Page	256
File Size	458033
Page Count	4
File Format	PDF
ISBN	0780342372
DOI	10.1109/ICSD.1998.709273
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-22
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage control Threshold voltage Current measurement Gain measurement Flash memory Dielectric devices Testing Plasma applications Plasma devices Etching
Content Type	Text
Resource Type	Article

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