NDLI: Multi-thread IO in high quality digital broadcasting system

Content Provider	IEEE Xplore Digital Library
Author	Shuo Wang Jiangling Zhang Dan Feng
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Huazhong Univ. of Sci. & Technol., Wuhan, China (Shuo Wang; Jiangling Zhang; Dan Feng)
Abstract	To meet the need of performance in high quality digital broadcasting systems (HQDBS), such as high IO width, no frame loss, and seamless switch etc, an algorithm called MPPDIO (multi-thread parallel prefetch Direct IO) is proposed in this paper. The size of the sharing buffer between multi-threads is modeled and calculated. To investigate the validation of the MPPDIO algorithm, the I/O performances are analyzed and compared when adopting a traditional pre-cache sequence algorithm and adopting the MPPDIO algorithm, and a set of comparable experiments is proceeded. Analysis and test results indicate that the traditional pre-cache sequence algorithm can't meet the need of performance, and the MPPDIO algorithm not only can perfectly satisfy the performance requirements but also can improve the utilization of disk I/O channel and reduce the load of CPU. The MPPDIO algorithm can also meet the requirements of digital broadcasting on HDTV (high definition television), which needs the same performance as the HQDBS.
Sponsorship	China Comput. Federation IEEE Comput. Soc. Beijing Center IEEE Comput. Soc. Tech. Committee on Distributed Process. Shanghai Comput. Soc
Starting Page	442
Ending Page	445
File Size	212768
Page Count	4
File Format	PDF
ISBN	0769520332
DOI	10.1109/ICCNMC.2003.1243087
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-10-20
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	TV broadcasting Streaming media Switches Digital video broadcasting Performance analysis Algorithm design and analysis HDTV Testing Video compression Multimedia communication
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Multi-thread VLIW processor architecture for HDTV decoding

A design of a streaming system for interactive television broadcast

A real-time HDTV video decoder

Performance of desktop software MPEG-2 TS decoder

Transmission of system information and additional service data for digital HDTV broadcasting

Personalized iDTV Program in Multimedia Home Platform

Effective multi-program broadcasting of prerecorded video using VBR MPEG-2 coding

University Library VOD System Based on Campus Network

Laboratory Tests for testing DVB-T2 mobile performance

Multi-thread IO in high quality digital broadcasting system

Similar Documents

Multi-thread VLIW processor architecture for HDTV decoding

A design of a streaming system for interactive television broadcast

A real-time HDTV video decoder

Performance of desktop software MPEG-2 TS decoder

Transmission of system information and additional service data for digital HDTV broadcasting

Personalized iDTV Program in Multimedia Home Platform

Effective multi-program broadcasting of prerecorded video using VBR MPEG-2 coding

University Library VOD System Based on Campus Network

Laboratory Tests for testing DVB-T2 mobile performance

Multi-thread IO in high quality digital broadcasting system