NDLI: VLSI parallel and distributed computation algorithms for discrete cosine transform processors

Content Provider	IEEE Xplore Digital Library
Author	Sung, T.-Y.
Copyright Year	1990
Description	Author affiliation: Telecommun. Lab., Minist. of Commun., Chungli, Taiwan (Sung, T.-Y.)
Abstract	A VLSI parallel and distributed computation algorithm has been proposed and mapped onto a VLSI architecture for a 1-D discrete cosine transform (DCT) involving the symmetry property. In this 1-D DCT processor architecture, there are (log/sub 2/N+1) DCT processor units (PUs) required for computation of a frame of N-point data with a time complexity of O(N). Further, a 2-D DCT processor architecture has been proposed with the input buffer of an (M1) 1-D N-point DCT processor array required for computation of the M frames of N-point input data and the output buffer of a (1N) 1-D M-point DCT processor array required for permutation of the N frames of M-point output data, so that the total number of DCT PUs require is (M(log/sub 2/N+1)+N(log/sub 2/M+1)) with a time complexity of O(M+N). Both of the 1-D and 2-D DCT processor architectures can be controlled by firmware; hence they are more flexible, efficient, and fault tolerant and, therefore, very suitable for VLSI implementation.<>
Starting Page	68
Ending Page	72
File Size	316115
Page Count	5
File Format	PDF
ISBN	0818620307
DOI	10.1109/PCCC.1990.101602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-03-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Very large scale integration Concurrent computing Distributed computing Discrete cosine transforms Discrete transforms Signal processing algorithms Kernel Discrete Fourier transforms Telecommunication computing Computer architecture
Content Type	Text
Resource Type	Article

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