NDLI: System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems

Content Provider	IEEE Xplore Digital Library
Author	Sandoval, N. Mackin, C. Whitsitt, S. Lysecky, R. Sprinkle, J.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA (Sandoval, N.; Mackin, C.; Whitsitt, S.; Lysecky, R.; Sprinkle, J.)
Abstract	The complexity of embedded applications has led to highly configurable algorithms and standards that support a wide range of data inputs. Design time optimization of these algorithms is not possible due to combinatorial explosion of data configurations - or data profiles - that can be observed at runtime. To address these challenges, data adaptable design methodologies can be utilized to directly model the correlation of data profiles and algorithmic requirements. This approach enables a reconfigurable implementation that adapts the system execution at runtime to utilize profile-specific hardware tasks in response to changes in the data profile of the current input data. In this paper, we present a simulation-based methodology and heuristic search methodology for determining system configurations considering available hardware accelerators and the sizes of FIFO queues within those accelerators to determine Pareto optimal configurations for system throughput and area. We further present a hardware/software communication wrapper and middleware to support seamless communication between software and hardware tasks.
Sponsorship	IEEE Comput. Soc.
Starting Page	59
Ending Page	68
File Size	470332
Page Count	10
File Format	PDF
e-ISBN	9780769549910
DOI	10.1109/ECBS.2013.25
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Data models Runtime Middleware Firing Field programmable gate arrays hardware/software communication middleware Data adaptability model-based design hardware/software codesign
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Hardware/Software Communication Middleware for Data Adaptable Embedded Systems

Efficient reconfiguration methods to enable rapid deployment of runtime reconfigurable systems

Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems

Runtime hardware/software task transition scheduling for data-adaptable embedded systems

Codesign of embedded systems based on Java and reconfigurable hardware components

A hardware and software programmable platform for industrial embedded application

VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems

Zebra: Building Efficient Network Message Parsers for Embedded Systems

Modeling of Data Adaptable Reconfigurable Embedded Systems

System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems

Similar Documents

Hardware/Software Communication Middleware for Data Adaptable Embedded Systems

Efficient reconfiguration methods to enable rapid deployment of runtime reconfigurable systems

Automated Software Generation and Hardware Coprocessor Synthesis for Data-Adaptable Reconfigurable Systems

Runtime hardware/software task transition scheduling for data-adaptable embedded systems

Codesign of embedded systems based on Java and reconfigurable hardware components

A hardware and software programmable platform for industrial embedded application

VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems

Zebra: Building Efficient Network Message Parsers for Embedded Systems

Modeling of Data Adaptable Reconfigurable Embedded Systems

System Throughput Optimization and Runtime Communication Middleware Supporting Dynamic Software-Hardware Task Migration in Data Adaptable Embedded Systems