NDLI: ViDL: A Versatile ISA Description Language

Content Provider	IEEE Xplore Digital Library
Author	Dreesen, Ralf
Copyright Year	2012
Abstract	Application specific processors as part of systems-on-a-chip (SoCs) have become increasingly popular in recent years. The need for efficient development of such processors raises the demand for simple and reliable tools and respective specification languages. This paper presents the Versatile Instruction Set Architecture Description Language (ViDL), to formally define (application specific) instruction sets. Simulators and processor implementations are then generated from such specifications. The language features functional and domain specific concepts to allow for rapid and simple specification of realistic instruction sets. In contrast to related approaches, ViDL strictly abstracts from micro architectural aspects, such as the instruction pipeline and hazard resolution. These aspects are shifted from the developer to a generator, which greatly simplifies specification and increases reliability. From the very same ViDL specification, we can automatically generate consistent instruction set simulators (40 - 140 MIPS), web-based simulators, and a set of processors with different pipeline structures (2-7 stages, 300-650 MHz). Formalization of instruction sets (ARM, MIPS, Power, SRC, and Core VA) in ViDL has shown to be simple. It took only between 2 month and 90 minutes.
Starting Page	222
Ending Page	231
File Size	399405
Page Count	10
File Format	PDF
ISBN	9781467309127
DOI	10.1109/ECBS.2012.49
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-04-11
Publisher Place	Serbia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semantics Instruction sets Registers Generators Pipelines Microarchitecture Instruction Set ViDL ISA DSL Processor Simulator Generator ASIP Language
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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