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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bernardi, P. Rebaudengo, M. Reorda, M.S. |
| Copyright Year | 2003 |
| Description | Author affiliation: Dipt. di Autom. e Inf., Politecnico di Torino, Italy (Bernardi, P.; Rebaudengo, M.; Reorda, M.S.) |
| Abstract | This paper addresses the issue of diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper. The proposed solution exploits a hardware-implemented compression method that minimizes the amount of data to be transferred from the core to the ATE. The proposed solution takes into account several constraints existing in an industrial environment, such as reducing the time and area overheads required for diagnosis, and minimizing the cost of the external ATE. Experimental results are provided allowing evaluating the benefits and limitations of the adopted solution. |
| Sponsorship | IEEE Ind. Electron. Soc. UNINOVA & Univ. Nova de Lisboa-FCT- DEE |
| Starting Page | 417 |
| Ending Page | 421 |
| File Size | 329471 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780379373 |
| DOI | 10.1109/ETFA.2003.1247736 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-09-16 |
| Publisher Place | Portugal |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Data mining System-on-a-chip System testing Logic testing Fault diagnosis Costs Read-write memory Built-in self-test Lakes Semiconductor memory |
| Content Type | Text |
| Resource Type | Article |
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