NDLI: Novel multi-layer through-die connections for package to chip power and ground connections

Content Provider	IEEE Xplore Digital Library
Author	Kommera, S. Woods, W. Krusius, J.P.
Copyright Year	2003
Description	Author affiliation: Cornell University, Ithaca, NY, USA (Kommera, S.; Woods, W.; Krusius, J.P.)
Abstract	Novel high-density through-die connections from the front to the back of a silicon die are described. Single-diameter front-to-back through-die connections have previously been explored for various applications. The authors have explored a two-level version of multi-diameter through-die hole connections for high-density chip-to-package and on-chip power and ground distribution application. In conbast, front-side area-array chip-to-package connections, for example C4, are used for conventional power and ground distribution for high-performance microprocessor applications. Through-die power and ground distribution has the potential to save several thousand front-side power and ground chip-to-package connections in hture high- performance microprocessors by connecting power and ground primarily to backside conductor planes on the silicon die and fiom there to the package. This approach will reduce the Wiring demand on the die front-side, minimize effective on-chip inductances of nearest neighbor power/ground return paths, reduce simultaneous switching noise, and provide significant amounts of on-chip decoupling capacitance. Two-level through-die hole test structures have heen designed, fabrication processes developed and resulting interconnect structures characterized. Conductive thin-film sidewall coatings have been accomplished with conformal Tungsten and in-situ doped polysilicon CVD. New CMP based patterning has heen developed to pattem the conductive films on perforated die. A Process flow for inclusion of the through-die process into a conventional CMOS process is described. Single chip packages for die with through-die power and ground distribution architectures are proposed.
Starting Page	620
Ending Page	626
File Size	818799
Page Count	7
File Format	PDF
ISBN	0780377915
ISSN	05695503
DOI	10.1109/ECTC.2003.1216345
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-05-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Packaging Silicon Wiring Etching Microprocessors Testing Fabrication Conductive films Routing
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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