NDLI: A nonvolatile charge-addressed memory (NOVCAM) cell

Content Provider	IEEE Xplore Digital Library
Author	White, M.H. Lampe, D.R. Fagan, J.L. Barth, D.A.
Copyright Year	1974
Description	Author affiliation: Westinghouse Defense and Electronic Systems Center, Advanced Technology Laboratory, Baltimore, Maryland 21203, USA (White, M.H.; Lampe, D.R.; Fagan, J.L.; Barth, D.A.)
Abstract	The combination of CCD and MNOS devices for signal transfer and nonvolatile storage has been discussed by several workers 1–3. In the initial attempt to combine these structures 1 the MNOS storage site was located inside a stepped dielectric, 2φ, CCD shift register. Certain problems were encountered such as inadequate charge handling capability which resulted in poor write characteristics, ineffective write/inhibit operation since high voltage clocks (for good transfer efficiency) caused spurious write operation, poor read operation due to the large access time to first bit and small detection window, and degraded memory retention caused by a small write window and read-disturb effects. To alleviate these problems a compact, nonvolatile, charge-addressed memory (NOVCAM) cell was introduced 2 for block oriented random access memory (BORAM) applications. The NOVCAM cell is composed of a CCD shift register and a thin-oxide MNOS memory structure in parallel with the register to provide separate locations for signal address and storage. Charge is transferred from the CCD shift register to the MNOS structure with a transfer gate φT which results in a collapse of the surface potential beneath the MNOS structure. Once the surface potential is collapsed, the oxide electric field strength increases and the tunneling of signal charge commences from the surface channel into deep traps located near the Si02/Si3N4 interface. The read-out is nondestructive (NDRO) and accomplished through the control action of the MNOS surface potential which gates the parallel charge injection from a $P^{+}$ source diffusion into the CCD shift register.
Starting Page	115
Ending Page	118
File Size	2082162
Page Count	4
File Format	PDF
ISSN	01631918
DOI	10.1109/IEDM.1974.6219627
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1974-12-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge coupled devices Clocks Substrates Capacitance Registers
Content Type	Text
Resource Type	Article
Subject	Materials Chemistry Electronic, Optical and Magnetic Materials Condensed Matter Physics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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